![]() The next state is 0100 by the statement Nextstate <= Currstate(0) & Currstate(N-1 DOWNTO 1). What happens is on reset the currstate is 1000 as explained above. The first statement picks the bit-0 of currstate and concatenate it with the rest. The next two statements are the real brain of the whole logic. If so Nextstate value is assigned to Currstate. This statement checks if enable is active. So the system is reset and Currstate value is “1000”. If the reset is not 1 then the control jumps to ELSIF(En=’1′) statement. This statement means if reset is 1 then Currstate ‘1’,OTHERS =>’0′) which assigns Currstate=”1000″. ![]() If arrived the control moves in the if statement and checks the next condition Rst=’1′. In the process block the statement Clk = ‘1’ AND Clk’EVENT checks if the positive edge of the clock is arrived. In body of the architecture a process is generated. These signals must be of the same size of variable since they hold the output. Current state and next state signals are defined. In the architecture i made an FSM(finite state machine) for the logic and implemented it.
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